1. Field of the Invention
The invention relates generally to microelectronics devices, and more particularly, to microelectronics packaging.
2. Description of the Related Art
Flip chip microelectronic assembly is the direct electrical connection of face-down silicon dies onto chip carriers, by means of conductive bumps on chip bond pads. Flip chip microelectronic assembly will be described with reference to FIG. 1a, which depicts the prior art. Bumps 118, which are first level interconnects, could be solder based bumps, or pure copper, or any other form of conductive bumps 118 connect the integrated circuits (silicon die) 110 to a chip carrier 120. Bond pads 114, called under bump metallization (UBM), which consist of a few layers of metals, provide a pad metallurgy that protects the integrated circuit (IC) chip 110, while making a good mechanical and electrical connection to the solder bump 118. In current applications, the UBM 114 and bump 118 lie on top of a thick soft polymer layer 112 with a small via 116 connecting the bump 118 to the underlying finer metal wires (called back-end-of-line structure (BEOL)). In prior art microelectronic assemblies, the via 116, UBM 114, and solder bump 118 are co-centered.
One problem associated with prior art microelectronic assemblies, and more specifically a co-centered via 116, UBM 114, and bump 118 is that during chip 110/chip carrier 120 assembly, bumps 118 in the peripheral regions, e.g. corners, of the chip 110, cause delamination in the BEOL because the vias 116 in the peripheral regions of the chip 110 undergo more tensile stress than vias 116 located towards the center of the chip 110.
Chip 110/chip carrier 120 assembly rotates the bump 118 such that one side of bump 118 pulls away from the silicon chip 110, i.e. tensile stress, and other side of the bump pushes into the silicon chip 110, i.e. compressive stress. Bumps 118 located at the center of the chip 110 experience less rotation than bumps 118 located at the peripheral regions for the chip 110. Therefore, the bumps 118 located at the center of the chip 110 suffer less BEOL delamination than bumps 118 located in the peripheral regions of the chip 110.
FIG. 1b depicts the forces applied to the prior art microelectronics assembly 100 during chip attach for a bump 118 located in the peripheral regions of the silicon chip 110. Fx, Fy depict the net forces applied to the bump 118 during chip attach, and f(x) depicts the tensile or compressive forces applied along the UBM 114 and chip 110 interface. The force f(x) transitions from compressive to tensile stress along the UBM 114 and chip 110 interface. When the via 116, UBM 114, and bump 118 are co-centered, as shown in FIG. 1a, the via 116 is located at a position of tensile stress as shown in FIG. 1b. 
A rigid connection between the bump 118 and the via 116 facilitates the force transfer from the chip carrier 120 to the region directly under the via 116. A thick soft polymer 112 provides a stress buffer to the BEOL region underneath the bump 118 edge, however the region under the via 116 does not have a stress buffer. Therefore, the via 116 experiences the full effect of the stress under the bump 118, which when the via 116 is centered with the bump 118, is tensile as depicted in FIG. 1b. Such tensile force causes delamination in the BEOL.
As microelectronics technology evolves, low k dielectric materials are more frequently utilized. Low k dielectric is even further prone to delamination in the BEOL. Therefore, a solution to delamination in the BEOL for bumps located in the peripheral regions of the microelectronics chip becomes ever more critical.
FIG. 1c depicts a top view of a chip 110 with the prior art microelectronics assembly 100. The chip includes multiple horizontal rows of UBM 114 with an included via 116. The geometric center of each via 116 is centered with the geometric center of the UBM 114, which is in turn aligned with the centerline of the horizontal row in which the UBM 114 and included via 116 lie.
What is needed in the art is an improved microelectronics chip package that reduces delamination in the BEOL associated with bumps located in the peripheral regions of a microelectronics chip.